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MYSON TECHNOLOGY
MTV212M64i (Rev 0.9)
8051 Embedded Monitor Controller Flash Type with ISP
FEATURES
* * * * * * * * * * * * *
8051 core, 12MHz operating frequency. 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming(ISP). Maximum 14 channels of 5V open-drain PWM DAC. Maximum 32 bi-directional I/O pins. SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment and programmable clamp pulse output. Built-in self-test pattern generator with four free-running timings. Built-in low power reset circuit. Compliant with VESA DDC1/2B/2Bi/2B+ standard. Dual slave IIC addresses. Single master IIC interface for internal device communication. 4-channel 6-bit ADC. Watchdog timer with programmable intervals. 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M64i micro-controller is an 8051 CPU core embedded device especially tailored to Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P0.07 RD WR
ALE INT1
P1.0-7 P2.0-2,P2.4-7
P3.2-0
P3.4-5 RST X1 X2
P0.07 RD WR
ALE INT1
XFR
H/VSYNC CONTROL
STOUT HBLANK VBLANK HSYNC VSYNC HCLAMP HALFV HALFH
8051
AD0-2
ADC
14 CHANNEL PWM DAC
ISCL ISDA HSCL HSDA
DDC & IIC INTERFACE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
2000/11/16
MYSON TECHNOLOGY
PIN CONNECTION
MTV212M64i
(Rev 0.9)
Note: As long as the pin sequence is not changed, the pin-out of 42 pin SDIP is negotiable according to customers'demand.
DA2/P5.2 DA1/P5.1 DA0/P5.0 RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P2.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P2.7/DA13 P2.6/DA12 P2.5/DA11 P2.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7
MTV212M64i 40 Pin PDIP
DA0/P5.0 NC NC NC
DA2/P5.2 DA1/P5.1
DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC
DA2/P5.2 DA1/P5.1 DA0/P5.0 NC NC NC RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P2.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
MTV212M64i 42 Pin SDIP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P2.6/DA12 P2.5/DA11 P2.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 P1.5
40 41 42 43 44 1 2 3 4 5 6 RST VDD P2.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P2.2/AD2 P1.0 7 8 9 10 11 12 13 14 15 16 17
MTV212M64i 44 Pin PLCC
39 38 37 36 35 34 33 32 31 30 29
DA8/HALFH DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P2.7/DA13 P2.6/DA12 P2.5/DA11 P2.4/DA10 HSCL/P3.0/Rxd
28 27 26 25 24 23 22 21 20 19 18 P1.5 P1.4 P1.3 P1.2 P3.2/INT0 P1.1 HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6
Revision 0.9
-2-
2000/11/17
MYSON TECHNOLOGY
PIN DESCRIPTION
Name DA2/P5.2 DA1/P5.1 DA0/P5.0 RST VDD P2.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P2.2/AD2 P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.1/AD1 P2.0/AD0 HSDA/P3.1/Txd HSCL/P3.0/Rxd P2.4/DA10 P2.5/DA11 P2.6/DA12 P2.7/DA13 DA6/P5.6 DA7/HCLAMP VBLANK/P4.0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC Type I/O I/O I/O I I/O O I I/O I/O O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I I Description
MTV212M64i
(Rev 0.9)
PWM DAC output (5V open drain) / General purpose I/O (5V open drain) PWM DAC output (5V open drain) / General purpose I/O (5V open drain) PWM DAC output (5V open drain) / General purpose I/O (5V open drain) Active high reset Positive Power Supply General purpose I/O (CMOS output or 8051 standard) / ADC Input Ground Oscillator output Oscillator input Master IIC data (5V open drain) / General purpose I/O (8051 standard) / T0 Master IIC clock (5V open drain) / General purpose I/O (8051 standard) / T1 Self-test video output (CMOS) / General purpose Output (CMOS) General purpose I/O (CMOS output or 8051 standard) / ADC Input General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose Input / INT0 General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) General purpose I/O (CMOS output or 8051 standard) / ADC Input General purpose I/O (CMOS output or 8051 standard) / ADC Input Slave IIC data (5V open drain) / General purpose I/O (8051 standard) / Txd Slave IIC clock (5V open drain) / General purpose I/O (8051 standard) / Rxd General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS) General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS) General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS) General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS) PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O) PWM DAC output (CMOS) / Hsync clamp pulse output (CMOS) Vertical blank (CMOS) / General purpose Output (CMOS) Horizontal blank (CMOS) / General purpose Output (CMOS) PWM DAC output (5V open drain) / vsync half freq. output (5V open drain) PWM DAC output (5V open drain) / hsync half freq. output (5V open drain) PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O) PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O) PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O) Horizontal SYNC or Composite SYNC Input Vertical SYNC input
Revision 0.9
-3-
2000/11/17
MYSON TECHNOLOGY
PIN CONFIGURATION
MTV212M64i
(Rev 0.9)
A "CMOS output pin" means it can sink and drive at least 4mA current. It' not recommended to use such pin s as input function. A "5V open drain pin" means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as input or output function and needs an external pull up resistor. A "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drive at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load devices.
4mA
10uA
120uA
2 OSC period delay 4mA Output Data Input Data
8051 Standard Pin
Pin
4mA
CMOS Output Pin
Output Data 4mA Pin
No Current
5V Open Drain Pin
Input Data 4mA Output Data Pin
Revision 0.9
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2000/11/17
MYSON TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core MTV212M64i includes all 8051 functions with the following exceptions:
MTV212M64i
(Rev 0.9)
1.1 The external RAM access is restricted to XFRs/AUXRAM within the MTV212M64i. 1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor special application. 1.3 INT1 input pin is not provided, it is connected to special interrupt sources. 1.4 Port2 is shared by special function pins. In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map, please refer to 8051 spec.
2. Memory Allocation 2.1 Internal Special Function Registers (SFR) The SFR is a group of registers that are the same as standard 8051. 2.2 Internal RAM There are total 256 bytes internal RAM in MTV212M64i, same as standard 8052. 2.3 External Special Function Registers (XFR) The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access these registers. 2.4 Auxiliary RAM (AUXRAM) There are a total of 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is divided into six banks, selected by XBANK register. Program can initialize Ri value and use "MOVX" instruction to access the AUXRAM.
FFh
Internal RAM
Accessible by indirect addressing only (Using MOV A,@Ri instruction)
SFR
Accessible by direct addressing
FFh
AUXRAM
Accessible by indirect external RAM addressing (XBANK=0)(Using MOVX A,@Ri instruction) ... .. XBANK= 2,3,4,5
AUXRAM
Accessible by indirect external RAM addressing (XBANK=5)(Using MOVX A,@Ri instruction)
80h 7Fh
Internal RAM
Accessible by direct and indirect addressing
80h 7Fh
XFR
Accessible by indirect external RAM addressing (Using MOVX A,@Ri instruction
00h
00h
Revision 0.9
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2000/11/17
MYSON TECHNOLOGY
3. Chip Configuration
MTV212M64i
(Rev 0.9)
The Chip Configuration registers define the chip pins function, as well as the connection, configuration and frequency of the functional blocks. Reg name PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION OPTION XBANK addr 30h (w) 31h (w) 32h (w) 3Ah (w) 3Bh (w) 3Ch (w) 33h (w) 34h (w) 35h (r/w) bit7 DA13E HIICE COP17 COP27 PWMF bit6 DA12E P56E IIICE COP16 COP26 DIV253 bit5 DA11E P55E HLFVE COP15 COP25 FclkE bit4 DA10E P54E HLFHE COP14 COP24 IICpass bit3 AD3E P53E HCLPE COP13 COP23 COP56 ENSCL bit2 AD2E P52E P42E COP12 COP22 COP55 Msel Xbnk2 bit1 AD1E P51E P41E COP11 COP21 COP54 MIICF1 SlvAbs1 Xbnk1 bit0 AD0E P50E P40E COP10 COP20 COP53 MIICF0 SlvAbs0 Xbnk0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset) DA13E = 1 Pin "P2.7/DA13" is DA13. =0 Pin "P2.7/DA13" is P2.7. DA12E = 1 Pin "P2.6/DA12" is DA12. =0 Pin "P2.6/DA12" is P2.6. DA11E = 1 Pin "P2.5/DA11" is DA11. =0 Pin "P2.5/DA11" is P2.5. DA10E = 1 Pin "P2.4/DA10" is DA10. =0 Pin "P2.4/DA10" is P2.4. AD3E = 1 Pin "P2.3/AD3" is AD3. =0 Pin "P2.3/AD3" is P2.3. AD2E = 1 Pin "P2.2/AD2" is AD2. =0 Pin "P2.2/AD2" is P2.2. AD1E = 1 Pin "P2.1/AD1" is AD1. =0 Pin "P2.1/AD1" is P2.1. AD0E = 1 Pin "P2.0/AD0" is AD0. =0 Pin "P2.0/AD0" is P2.0. P56E = 1 Pin "DA6/P5.6" is P5.6. =0 Pin "DA6/P5.6" is DA6. P55E = 1 Pin "DA5/P5.5" is P5.5. =0 Pin "DA5/P5.5" is DA5. P54E = 1 Pin "DA4/P5.4" is P5.4. =0 Pin "DA4/P5.4" is DA4. P53E = 1 Pin "DA3/P5.3" is P5.3. =0 Pin "DA3/P5.3" is DA3. P52E = 1 Pin "DA2/P5.2" is P5.2. =0 Pin "DA2/P5.2" is DA2. P51E = 1 Pin "DA1/P5.1" is P5.1. =0 Pin "DA1/P5.1" is DA1. P50E = 1 Pin "DA0/P5.0" is P5.0. =0 Pin "DA0/P5.0" is DA0. HIICE = 1 Pin "HSCL/P3.0/Rxd" is HSCL; pin "HSDA/P3.1/Txd" is HSDA. =0 Pin "HSCL/P3.0/Rxd" is P3.0/Rxd; pin "HSDA/P3.1/Txd" is P3.1/Txd. IIICE = 1 Pin "ISDA/P3.4/T0" is ISDA; pin "ISCL/P3.5/T1" is ISCL. =0 Pin "ISDA/P3.4/T0" is P3.4/T0; pin "ISCL/P3.5/T1" is P3.5/T1. HLFVE = 1 Pin "DA9/HALFV" is VSYNC half frequency output. Revision 0.9 -62000/11/17
MYSON TECHNOLOGY
=0 HLFHE = 1 =0 HCLPE = 1 =0 P42E = 1 =0 P41E = 1 =0 P40E = 1 =0 COP17 = 1 =0 COP16 = 1 =0 COP15 = 1 =0 COP14 = 1 =0 COP13 = 1 =0 COP12 = 1 =0 COP11 = 1 =0 COP10 = 1 =0 COP27 = 1 =0 COP26 = 1 =0 COP25 = 1 =0 COP24 = 1 =0 COP23 = 1 =0 COP22 = 1 =0 COP21 = 1 =0 COP20 = 1 =0 COP56 = 1 =0 COP55 = 1 =0 COP54 = 1 =0 COP53 = 1 =0 Revision 0.9
MTV212M64i
(Rev 0.9)
Pin "DA9/HALFV" is DA9. Pin "DA8/HALFH" is HSYNC half frequency output. Pin "DA8/HALFH" is DA8. Pin "DA7/HCLAMP" is HSYNC clamp pulse output. Pin "DA7/HCLAMP" is DA7. Pin "STOUT/P4.2" is P4.2. Pin "STOUT/P4.2" is STOUT. Pin "HBLANK/P4.1" is P4.1. Pin "HBLANK/P4.1" is HBLANK. Pin "VBLANK/P4.0" is P4.0. Pin "VBLANK/P4.0" is VBLANK. Pin "P1.7" is CMOS Output. Pin "P1.7" is 8051 standard I/O. Pin "P1.6" is CMOS Output. Pin "P1.6" is 8051 standard I/O. Pin "P1.5" is CMOS Output. Pin "P1.5" is 8051 standard I/O. Pin "P1.4" is CMOS Output. Pin "P1.4" is 8051 standard I/O. Pin "P1.3" is CMOS Output. Pin "P1.3" is 8051 standard I/O. Pin "P1.2" is CMOS Output. Pin "P1.2" is 8051 standard I/O. Pin "P1.1" is CMOS Output. Pin "P1.1" is 8051 standard I/O. Pin "P1.0" is CMOS Output. Pin "P1.0" is 8051 standard I/O. Pin "P2.7/DA13" is CMOS data Output. Pin "P2.7/DA13" is 8051 standard I/O or CMOS PWM DAC Output. Pin "P2.6/DA12" is CMOS data Output. Pin "P2.6/DA12" is 8051 standard I/O or CMOS PWM DAC Output. Pin "P2.5/DA11" is CMOS data Output. Pin "P2.5/DA11" is 8051 standard I/O or CMOS PWM DAC Output. Pin "P2.4/DA10" is CMOS data Output. Pin "P2.4/DA10" is 8051 standard I/O or CMOS PWM DAC Output. Pin "P2.3/AD3" is CMOS data Output. Pin "P2.3/AD3" is 8051 standard I/O or ADC Input. Pin "P2.2/AD2" is CMOS data Output. Pin "P2.2/AD2" is 8051 standard I/O or ADC Input. Pin "P2.1/AD1" is CMOS data Output. Pin "P2.1/AD1" is 8051 standard I/O or ADC Input. Pin "P2.0/AD0" is CMOS data Output. Pin "P2.0/AD0" is 8051 standard I/O or ADC Input. Pin "DA6/P5.6" is CMOS data Output. Pin "DA6/P5.6" is open drain I/O or CMOS PWM DAC. Pin "DA5/P5.5" is CMOS data Output. Pin "DA5/P5.5" is open drain I/O or CMOS PWM DAC. Pin "DA4/P5.4" is CMOS data Output. Pin "DA4/P5.4" is open drain I/O or CMOS PWM DAC. Pin "DA3/P5.3" is CMOS data Output. Pin "DA3/P5.3" is open drain I/O or CMOS PWM DAC. -72000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
OPTION (w) : Chip option configuration (All are "0" in Chip Reset). PWMF = 1 Selects 94KHz PWM frequency. =0 Selects 47KHz PWM frequency. DIV253 = 1 PWM pulse width is 253-step resolution. =0 PWM pulse width is 256-step resolution. FclkE = 1 Double CPU clock freq. IICpass = 1 HSCL/HSDA pin bypasses to ISCL/ISDA pin in DDC2 mode. =0 Separates Master and Slave IIC block. ENSCL = 1 Enables slave IIC block to hold HSCL pin low while MTV212M64i is unable to catch up the external master's speed. Msel =1 Master IIC block connects to HSCL/HSDA pins. =0 Master IIC block connects to ISCL/ISDA pins. MIICF1,MIICF0 = 1,1 Selects 400KHz Master IIC frequency. = 1,0 Selects 200KHz Master IIC frequency. = 0,1 Selects 50KHz Master IIC frequency. = 0,0 Selects 100KHz Master IIC frequency. SlvAbs1,SlvAbs0 : Slave address length of Slave IIC block A. = 1,0 5-bits slave address. = 0,1 6-bits slave address. = 0,0 7-bits slave address. XBANK (r/w) : Auxiliary RAM bank switch. Xbnk[2:0] =0 Selects AUXRAM bank 0. =1 Selects AUXRAM bank 1. =2 Selects AUXRAM bank 0. =3 Selects AUXRAM bank 1. =4 Selects AUXRAM bank 0. =5 Selects AUXRAM bank 1. 4. Extra I/O The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as both output and input for that the pin of Port5 is open drain type, users must write corresponding bit of Port5 to "1" in input mode. Reg name PORT4 PORT5 PORT4 (w) : PORT5 (r/w) : addr 38h (w) 39h (r/w) bit7 bit6 P56 bit5 P55 bit4 P54 bit3 P53 bit2 P42 P52 bit1 P41 P51 bit0 P40 P50
Port 4 data output value. Port 5 data input/output value.
5. PWM DAC Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output. If DIV253=0, the output will pulse low at least once even if the content of DAC register is FFH. Writing 00H to DAC register generates stable low output.
Revision 0.9
-8-
2000/11/17
MYSON TECHNOLOGY
Reg name DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 addr 20h (r/w) 21h (r/w) 22h (r/w) 23h (r/w) 24h (r/w) 25h (r/w) 26h (r/w) 27h (r/w) 28h (r/w) 29h (r/w) 2Ah (r/w) 2Bh (r/w) 2Ch (r/w) 2Dh (r/w) bit7 bit6
MTV212M64i
(Rev 0.9)
bit1 bit0
bit5 bit4 bit3 bit2 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13
DA0-13 (r/w) : The output pulse width control for DA0-13. * All of PWM DAC converters are centered with value 80h after power on. 6. H/V SYNC Processing The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC inputs presence check, frequency counting, polarity detection and control, as well as the protection of VBLANK output while VSYNC speeds up in high DDC communication clock rate. The present and frequency function block treat any pulse shorter than one OSC period as noise.
Digital Filter Present Check Vpre
Polarity Check & Freq. Count
Vfreq Vpol Vbpl
VSYNC CVSYNC XOR Vself Present Check CVpre XOR VBLANK
Digital Filter
Polarity Check & Sync Seperator Present Check & Freq. Count
Hpol
Hpre Hfreq Hbpl
Composite Pulse Insert XOR HSYNC Hself XOR HBLANK
H/V SYNC Processor Block Diagram
Revision 0.9
-9-
2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
6.1 Composite SYNC separation/insertion The MTV212M64i continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check, frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal. The MTV212M64i can also insert pulse to HBLANK output during composite active time of VSYNC. The insert pulse' width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The s HBLANK pulse can be disabled or enabled by setting "NoHins" control bit. 6.2 H/V Frequency Counter MTV212M64i can discriminate HSYNC/VSYNC frequency and save the information in XFRs. The 14 bits Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch. The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value changes or overflows. Table 4.2.1 and Table 4.2.2 show the HCNT/VCNT value under the operations of 12MHz.
6.2.1 H-Freq Table
H-Freq(KHZ) 1 2 3 4 5 6 7 8 9 10 11 12 31.5 37.5 43.3 46.9 53.7 60.0 68.7 75.0 80.0 85.9 93.8 106.3 Output Value (14 bits) 12MHz OSC (hex / dec) 0FDEh / 4062 0D54h / 3412 0B8Bh / 2955 0AA8h / 2728 094Fh / 2383 0854h / 2132 0746h / 1862 06AAh / 1706 063Fh / 1599 05D1h / 1489 0554h / 1364 04B3h / 1203
6.2.2 V-Freq Table
V-Freq(Hz) 1 2 3 4 5 6 56 60 70 72 75 85 Output value (12bits) 12MHz OSC (hex / dec) 45Ch / 1116 411h / 1041 37Ch / 892 364h / 868 341h / 833 2DFh / 735
6.3 H/V Present Check The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the CVpre flag interrupt may be disabled when S/W disables the composite function.
Revision 0.9
- 10 -
2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
6.4 H/V Polarity Detect The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the Vpol value changes. 6.5 Output HBLANK/VBLANK Control and Polarity Adjust The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz. The HBLANK/VBLANK shares the output pin with P4.1/ P4.0. 6.6 Self-Test Pattern Generator For testing purposes, this generator can generate 4 display patterns, which are positive cross-hatch, negative cross-hatch, full white, and full black (showed as following figure). The HBLANK output frequency of the pattern can be chosen to 95.2KHz, 63.5KHz, 47.6KHz and 31.75KHz. The VBLANK output frequency of the pattern is 72Hz or 60Hz. It is originally designed to support monitor manufacturers to do burn-in test, or offer end-users a reference to check the monitor. The output STOUT of the generator shares the output pin with P4.2.
Display Region
Positive cross-hatch
Negative cross-hatch
Full white
Full black
Revision 0.9
- 11 -
2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
MTV212M64i Self-Test Pattern Timing 63.5KHz, 60Hz 47.6KHz, 60Hz 31.7KHz, 60Hz Time H dots Time H dots Time H dots Hor. Total time (A) 15.75us 1280 21.0us 1024 31.5us 640 Hor. Active time (D) 12.05us 979.3 16.07us 783.2 24.05us 488.6 Hor. F. P. (E) 0.2us 16.25 0.28us 12 0.45us 9 SYNC pulse width (B) 1.5us 122 2us 90 3us 61 Hor. B. P. (C) 2us 162.54 2.67us 110 4us 81.27 Time 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms V lines 1024 962 3.87 3.87 54.2 Time 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms V lines 768 721.5 2.9 2.9 40.5 Time 16.66ms 15.65ms 0.063ms 0.063ms 0.882ms V lines 480 451 1.82 1.82 25.4
95.2KHz, 72Hz Time H dots 10.5us 1600 8.03us 1224 0.14us 21 1.0us 152 1.33us 203 Time 13.89ms 13.03ms 0.052ms 0.052ms 0.756ms V lines 1200 1126 4.5 4.5 65
Vert. Total time (O) Vert. Active time (R) Vert. F. P. (S) SYNC pulse width (P) Vert. B. P. (Q)
* 8 x 8 blocks of cross hatch pattern in display region. 6.7 HSYNC Clamp Pulse Output The HCLAMP output is active by setting "HCLPE" control bit. The leading edge position, pulse width and polarity of HCLAMP are S/W controllable. 6.8 VSYNC Interrupt The MTV212M64i checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag is set each time when MTV212M64i detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
Revision 0.9
- 12 -
2000/11/17
MYSON TECHNOLOGY
6.9 H/V SYNC Processor Register Reg name HVSTUS HCNTH HCNTL VCNTH VCNTL HVCTR0 HVCTR2 HVCTR3 INTFLG INTEN
MTV212M64i
(Rev 0.9)
addr bit7 bit6 bit5 bit4 bit3 bit2 40h (r) CVpre Hpol Vpol Hpre Vpre 41h (r) Hovf HF13 HF12 HF11 HF10 42h (r) HF7 HF6 HF5 HF4 HF3 HF2 43h (r) Vovf VF11 VF10 44h (r) VF7 VF6 VF5 VF4 VF3 VF2 40h (w) C1 C0 NoHins SelExH IVHlfH HlfHE 42h (w) Selft STF1 STF0 Rt1 43h (w) CLPEG CLPPO CLPW2 CLPW1 CLPW0 48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg 49h (w) EHPR EVPR EHPL EVPL EHF EVF
bit1 Hoff HF9 HF1 VF9 VF1 HBpl Rt0
bit0 Voff HF8 HF0 VF8 VF0 VBpl STE Vsync EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC. CVpre = 1 The extracted CVSYNC is present. =0 The extracted CVSYNC is not present. Hpol =1 HSYNC input is positive polarity. =0 HSYNC input is negative polarity. Vpol =1 VSYNC (CVSYNC) is positive polarity. =0 VSYNC (CVSYNC) is negative polarity. Hpre = 1 HSYNC input is present. =0 HSYNC input is not present. Vpre =1 VSYNC input is present. =0 VSYNC input is not present. Hoff* = 1 Off level of HSYNC input is high. =0 Off level of HSYNC input is low. Voff* = 1 Off level of VSYNC input is high. =0 Off level of VSYNC input is low. *Hoff and Voff are valid when Hpre=0 or Vpre=0. HCNTH (r) : H-Freq counter's high bits. Hovf =1 H-Freq counter is overflowed, this bit is cleared by H/W when condition removed. HF13 - HF8 : 6 high bits of H-Freq counter. HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits. Vovf =1 V-Freq counter is overflowed, this bit is cleared by H/W when condition removed. VF11 - 8 : 4 high bits of V-Freq counter. VCNTL (r) : V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0. C1, C0 = 1,1 Selects CVSYNC as the polarity, freq and VBLANK source. = 1,0 Selects VSYNC as the polarity, freq and VBLANK source. = 0,0 Disables composite function. = 0,1 H/W automatically switches to CVSYNC when CVpre=1 and VSpre=0. NoHins = 1 HBLANK has no insert pulse in composite mode. =0 HBLANK has insert pulse in composite mode. SelExH = 1 Input source of HLFHO is P1.0. =0 Input source HLFHO is HSYNC. Revision 0.9 - 13 2000/11/17
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IVHlfH = 1 =0 HlfHE = 1 =0 HBpl = 1 =0 VBpl = 1 =0 HLFHO is inverted. HLFHO is not inverted. HLFHO is half freq. of HSYNC/P1.0. HLFHO is same freq. of HSYNC/P1.0. Negative polarity HBLANK output. Positive polarity HBLANK output. Negative polarity VBLANK output. Positive polarity VBLANK output.
MTV212M64i
(Rev 0.9)
HVCTR2 (w) : Self-test pattern generator control. Selft =1 Enables generator. =0 Disables generator. STF1,STF0 = 1,1 95.2KHz(horizontal)/72Hz(vertical) output selected. = 1,0 63.5KHz(horizontal)/60Hz(vertical) output selected. = 0,1 47.6KHz(horizontal) /60Hz(vertical) output selected. = 0,0 31.75KHz(horizontal) /60Hz(vertical) output selected. Rt1,Rt0 = 0,0 Positive cross-hatch pattern output. = 0,1 Negative cross-hatch pattern output. = 1,0 Full white pattern output. = 1,1 Full black pattern output. STE =1 Enables STOUT output. =0 Disables STOUT output. HVCTR3 (w) : HSYNC clamp pulse control register. CLPEG = 1 Clamp pulse follows HSYNC leading edge. =0 Clamp pulse follows HSYNC trailing edge. CLPPO = 1 Positive polarity clamp pulse output. =0 Negative polarity clamp pulse output. CLPW2 : CLPW0 : Pulse width of clamp pulse is [(CLPW2:CLPW0) + 1] x 0.167 s for 12MHz X'tal selection. INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. HPRchg= 1 No action. =0 Clears HSYNC presence change flag. VPRchg= 1 No action. =0 Clears VSYNC presence change flag. HPLchg= 1 No action. =0 Clears HSYNC polarity change flag. VPLchg = 1 No action. =0 Clears VSYNC polarity change flag. HFchg = 1 No action. =0 Clears HSYNC frequency change flag. VFchg = 1 No action. =0 Clears VSYNC frequency change flag. Vsync = 1 No action. =0 Clears VSYNC interrupt flag.
INTFLG (r) : Interrupt flag. HPRchg= 1 Indicates a HSYNC presence change. VPRchg= 1 Indicates a VSYNC presence change. HPLchg= 1 Indicates a HSYNC polarity change. Revision 0.9 - 14 -
2000/11/17
MYSON TECHNOLOGY
VPLchg = 1 HFchg = 1 VFchg = 1 Vsync = 1
MTV212M64i
(Rev 0.9)
Indicates a VSYNC polarity change. Indicates a HSYNC frequency change or counter overflow. Indicates a VSYNC frequency change or counter overflow. Indicates a VSYNC interrupt.
INTEN (w) : Interrupt enable. EHPR = 1 Enables HSYNC presence change interrupt. EVPR = 1 Enables VSYNC presence change interrupt. EHPL = 1 Enables HSYNC polarity change interrupt. EVPL = 1 Enables VSYNC polarity change interrupt. EHF =1 Enables HSYNC frequency change / counter overflow interrupt. EVF =1 Enables VSYNC frequency change / counter overflow interrupt. EVsync = 1 Enables VSYNC interrupt. 7. DDC & IIC Interface 7.1 DDC1 Mode The MTV212M64i enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212M64i. The shift register fetches data byte from the DDC1 data buffer (DBUF) then sends it in 9 bits packet formats which includes a null bit (=1) as packet separator. The DBUF sets the DbufI interrupt flag when the shift register reads out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set. The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The DbufI interrupt can be masked or enabled by EDbufI control bit. 7.2 DDC2B Mode The MTV212M64i switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once MTV212M64i enters DDC2B mode, S/W can set IICpass control bit to allow HOST accessing EEPROM directly. Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other way to perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The slave address of Slave A block can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W chooses 5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2 LSB "xx" in XFR. This feature enables MTV212M64i to meet PC99 requirement. The MTV212M64i will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it. 7.3 Slave Mode IIC function Block The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using IIC protocol. There are 2 slave addresses to which MTV212M64i can respond. S/W may write the SLVAADR/SLVBADR register to determine the slave addresses. The Slave A address can be configured to 5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits. In receive mode, the block first detects IIC slave address matching the condition, then issues a SlvAMI/SlvBMI interrupt. If the matched address is Slave A, MTV212M64i will save 2 LSB bits of the matched address to SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time when the RCABUF/RCBBUF is loaded. If S/W is not able to read out the RCABUF/RCBBUF in time, the next byte in shift register will not be written to RCABUF/RCBBUF and the slave block returns NACK to the master. This feature guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W whether the data in RCABUF/RCBBUF is a word address. In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvAMI/SlvBMI interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is Slave A, and the data pre-stored in the TXABUF/TXBBUF is loaded into shift register, resulting in Revision 0.9 - 15 2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
TXABUF/TXBBUF emptying and generates a TXAI/TXBI (transmits buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte for the next transfer before shift register empties. A failure of this process will cause data corrupt. The TXAI/TXBI occurs every time when shift register reads out the data from TXABUF/TXBBUF. The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared. *Please see the attachments about "Slave IIC Block Timing". 7.4 Master Mode IIC Function Block The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit. The software program can access the external IIC device through this interface. Since the EDID/VDIF data and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212M64i only. In DDC2 mode and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL condition by reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the HSCL's rising edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0, MTV212M64i will hold HSCL low to isolate the access to EEPROM of the host. A summary of master IIC access is illustrated as follows. 7.4.1. To write IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV212M64i transmit this byte, a MbufI interrupt will be triggered. 4. Program can write MBUF to transfer next byte or set P bit to stop. * Please see the attachments about "Master IIC Transmit Timing". 7.4.2. To read IIC Device 1. Write MBUF the Slave Address. 2. Set S bit to Start. 3. After the MTV212M64i transmit this byte, a MbufI interrupt will be triggered. 4. Set or reset the MAckO flag according to the IIC protocol. 5. Read out MBUF the useless byte to continue the data transfer. 6. After the MTV212M64i receives a new byte, the MbufI interrupt is triggered again. 7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation. * Please see the attachments about "Master IIC Receive Timing". Reg name IICCTR IICSTUS IICSTUS INTFLG INTFLG INTEN MBUF RCABUF TXABUF SLVAADR RCBBUF TXBBUF SLVBADR DBUF Revision 0.9 addr 00h (r/w) 01h (r) 02h (r) 03h (r) 03h (w) 04h (w) 05h (r/w) 06h (r) 06h (w) 07h (w) 08h (r) 08h (w) 09h (w) 0Ah (w) bit7 DDC2 WadrB MAckIn TXBI ETXBI bit6 WadrA Hifreq RCBI bit5 bit4 bit3 bit2 MAckO bit1 bit0 P S SlvAlsb1 SlvAlsb0 MbufI MbufI EMbufI
ENSlvA
ENSlvB
SlvRWB SAckIn SLVS Hbusy SlvBMI TXAI RCAI SlvAMI DbufI SlvBMI SlvAMI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI Master IIC receive/transmit data buffer Slave A IIC receive buffer Slave A IIC transmit buffer Slave A IIC address Slave B IIC receive buffer Slave B IIC transmit buffer Slave B IIC address DDC1 transmit data buffer - 16 -
2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
IICCTR (r/w) : IIC interface control register. DDC2 = 1 MTV212M64i is in DDC2 mode, write "0" can clear it. =0 MTV212M64i is in DDC1 mode. MAckO = 1 In master receive mode, NACK is returned by MTV212M64i. =0 In master receive mode, ACK is returned by MTV212M64i. S, P = , 0 Start condition when Master IIC is not during transfer. = X, Stop condition when Master IIC is not during transfer. = 1, X Will resume transfer after a read/write MBUF operation. = X, 0 Force HSCL low and occupy the master IIC bus. * A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge. IICSTUS (r) : IIC interface status register. WadrB = 1 The data in RCBBUF is word address. WadrA = 1 The data in RCABUF is word address. SlvRWB = 1 Current transfer is slave transmit =0 Current transfer is slave receive SAckIn = 1 The external IIC host respond NACK. SLVS = 1 The slave block has detected a START, cleared when STOP detected. SlvAlsb1,SlvAlsb0 : The 2 LSB which host sends to Slave A block. MAckIn = 1 Master IIC bus error, no ACK received from the slave IIC device. =0 ACK received from the slave IIC device. Hifreq = 1 MTV212M64i has detected a higher than 200Hz clock on the VSYNC pin. Hbusy = 1 Host drives the HSCL pin to low. INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. SlvBMI = 1 No action. =0 Clears SlvBMI flag. SlvAMI = 1 No action. =0 Clears SlvAMI flag. MbufI = 1 No action. =0 Clears Master IIC bus interrupt flag (MbufI).
INTFLG (r) : TXBI RCBI
Interrupt flag. =1 Indicates the TXBBUF needs a new data byte, cleared by writing TXBBUF. =1 Indicates the RCBBUF has received a new data byte, cleared by reading RCBBUF. SlvBMI = 1 Indicates the slave IIC address B matches condition. TXAI = 1 Indicates the TXABUF needs a new data byte, cleared by writing TXABUF. RCAI = 1 Indicates the RCABUF has received a new data byte, cleared by reading RCABUF. SlvAMI = 1 Indicates the slave IIC address A matches condition. DbufI = 1 Indicates the DDC1 data buffer needs a new data byte, cleared by writing DBUF. MbufI = 1 Indicates a byte is sent/received to/from the master IIC bus.
INTEN (w) : Interrupt enable. ETXBI = 1 Enables TXBBUF interrupt. ERCBI = 1 Enables RCBBUF interrupt. ESlvBMI = 1 Enables slave address B match interrupt. ETXAI = 1 Enables TXABUF interrupt. ERCAI = 1 Enables RCABUF interrupt. ESlvAMI = 1 Enables slave address A match interrupt. Revision 0.9 - 17 2000/11/17
MYSON TECHNOLOGY
EDbufI = 1 EMbufI = 1 Mbuf (w) : Enables DDC1 data buffer interrupt. Enables Master IIC bus interrupt.
MTV212M64i
(Rev 0.9)
Master IIC data shift register, after START and before STOP condition, writing this register will resume transmission of MTV212M64i to the IIC bus. Master IIC data shift register, after START and before STOP condition, reading this register will resume receiving of MTV212M64i from the IIC bus. Slave IIC block A receives data buffer.
Mbuf (r) :
RCABUF (r) :
TXABUF (w) : Slave IIC block A transmits data buffer. SLVAADR (w) : Slave IIC block A's enable and address. ENslvA = 1 Enables slave IIC block A. =0 Disables slave IIC block A. bit6-0 : Slave IIC address A to which the slave block should respond. RCBBUF (r) : Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer. SLVBADR (w) : Slave IIC block B's enable and address. ENslvB = 1 Enables slave IIC block B. =0 Disables slave IIC block B. bit6-0 : Slave IIC address B to which the slave block should respond. 8. Low Power Reset (LVR) & Watchdog Timer When the voltage level of power supply is below 4.0V(+/-0.2V) for a specific period of time, the LVR will generate a chip reset signal. After the power supply is above 4.0V(+/-0.2V), LVR maintains in reset state for 144 Xtal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation. The WatchDog Timer automatically generates a device reset when it is overflowed. The interval of overflow is 0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer by set WCLR. 9. A/D converter The MTV212M64i is equipped with three 6-bit A/D converters, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64. Reg name ADC ADC WDT addr 10h (w) 10h (r) 18h (w) bit7 ENADC WEN bit6 bit5 bit4 bit3 bit2 bit1 SADC3 SADC2 SADC1 ADC convert Result WDT2 WDT1 bit0 SADC0 WDT0
WCLR
WDT (w) : WatchDog Timer control register. WEN =1 Enables WatchDog Timer. WCLR =1 Clears WatchDog Timer. WDT2: WDT0 = 0 Overflow interval = 8 x 0.25 sec. Revision 0.9 - 18 2000/11/17
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=1 =2 =3 =4 =5 =6 =7 ADC (w) : ADC control. ENADC =1 SADC0 =1 SADC1 =1 SADC2 =1 SADC3 =1 ADC (r) : Overflow interval = 1 x 0.25 sec. Overflow interval = 2 x 0.25 sec. Overflow interval = 3 x 0.25 sec. Overflow interval = 4 x 0.25 sec. Overflow interval = 5 x 0.25 sec. Overflow interval = 6 x 0.25 sec. Overflow interval = 7 x 0.25 sec. Enables ADC. Selects ADC0 pin input. Selects ADC1 pin input. Selects ADC2 pin input. No action.
MTV212M64i
(Rev 0.9)
ADC convert result.
10. In System Programming function (ISP) The Flash memory can be programmed by a specific WRITER in parallel mode, or by IIC Host in serial mode while the system is working. The feature of ISP is outlined as below: 1. 2. 3. 4. 5. 6. 7. 8. 9. Single 5V power supply for Program/Erase/Verify. Block Erase: 128 Byte at 4mS Whole Flash erase (Blank): 4mS Byte programming Cycle time: 60uS Read access time: 40ns Only one two-pin IIC bus (shared with DDC2) is needed for ISP in user/factory mode. IIC Bus clock rates up to 140KHz. Whole 32K byte Flash programming within 3 Sec. CRC check provides 100% coverage for all single/double bit errors.
After power on/Reset, the MTV212M64i is running the original ROM code. Once the S/W detects a ISP request (by key or IIC), S/W can accept the request following the steps below: 1. 2. 3. 4. 5. Clear watchdog to prevent reset during ISP period. Disable all interrupt to prevent CPU wake-up. Write IIC address of ISP slave to ISPSLV for communication. Write 93h to ISP enable register (ISPEN) to enable ISP. Enter 8051 idle mode.
When ISP is enabled, the MTV212M64i will disable WatchDog reset and switch the Flash interface to ISP host in 15-22.5uS. So S/W MUST enter idle mode immediately after enabling ISP. In the 8051 idle mode, PWM DACs and I/O pins keep running at its former status. There are 4 types of IIC bus transfer protocols in ISP mode. Command Write S-tttttt10k-cccccccck-AAAAAAAAk-P Command Read S-tttttt11k-ccccccccK-AAAAAAAAK-aaaaaaaaK-RRRRRRRRK-rrrrrrrrK-P Data Write S-tttttt00k-aaaaaaaak-ddddddddk- ... -ddddddddk-P Data Read S-tttttt00k-aaaaaaaak-(P)-S-tttttt01k-ddddddddK- ... -ddddddddK-P Revision 0.9 - 19 2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
, where S = start or re-start P = stop K = ack by host (0 or 1) k = ack by slave tttttt = ISP slave address cccccccc = command x = don't care X = not defined AAAAAAAA = Flash_address[15:8] aaaaaaaa = Flash_address[7:0] RRRRRRRR = CRC_register[15:8] rrrrrrrr = CRC_register[7:0] dddddddd = Flash_data cccccccc = 10100xxx Program cccccccc = 00110xxx Page Erase 128 bytes (Erase) cccccccc = 01101xxx Erase entire Flash (Blank) cccccccc = 11010xxx Clear CRC_register (Clr_CRC) cccccccc = 01001xxx Reset MTV212M64i (Reset_CPU) 10.1 ISP Command Write The 2nd byte of "Command Write" can define the operating mode of MTV212M64i in its "Data Write" stage, clear CRC register, or reset MTV212M64i. The 3rd byte of Command Write defines the page address (A15-8) of Flash memory. A Command Write may consist of 1,2 or 3 bytes. 10.2 ISP Command Read The 2nd byte echoes the current command in ISP slave. The 3rd and 4th byte reflect the current Flash address. The 5th and 6th byte report the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes. 10.3 ISP Data Write The 2nd byte defines the low address (A7-0) of Flash. After receiving the 3rd byte, the MTV212M64i will execute a Program/Erase/Blank command depending on the preceding "Command Write". The low address of Flash will increase every time when ISP slave acknowledges the data byte. The Blank/Erase command needs one data byte (content is "don' care"). The executing time is 4mS. During the 4mS period, the ISP t slave does not accept any command/data and returns non-ack to any IIC bus activity. The Program command may have 1-256 data bytes. The program cycle time is 60us. If the ISP slave is unable to complete the program cycle in time, it will return non-ack to the following data byte. In the meantime, the low address does not increase and the CRC does not count the non-acked data byte. A Data Write may consist of 1,2 or more bytes. Data Write (Blank/Erase) S-tttttt00k-aaaaaaaak-ddddddddk-P ... S-ttttttxxk|-----Min. 4mS----| Data Write (Program) S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... |Min. 60uS| 10.4 ISP Data Read The 1st and 2nd byte are the same as "Data Write" to define the low address of Flash. Between the 2nd and 3rd byte, the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave sends the data byte of Flash to ISP Host. The low address automatically increases every time when data byte is transferred. 10.5 Cyclic Redundancy Check (CRC) To shorten the verify time, the ISP slave providse a simple way to check whether data error occurs during the program data transfer. After the ISP Host sends a lot of data bytes to ISP slave, Host can use Command Read to check result of CRC register instead of reading every byte in Flash. The CRC register counts every data byte which ISP slave acknowledges during "Data Write" period. However, the low address byte and the data byte of Erase/Blank are not counted. The Clear CRC command will write all "1" to the 16-bit CRC register. For CRC generation, the 16-bit CRC register is seeded with all "1" pattern (by device reset or Clear CRC command). The data byte shifted into the CRC register is Msb first. The real implementation is described as follows: Revision 0.9 - 20 2000/11/17
MYSON TECHNOLOGY
MTV212M64i
(Rev 0.9)
CRCin = CRC[15]^DATAin; CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin}; Where ^ = XOR example: data_byte F6H 28H C3H
CRC_register_remainder FFFFH FF36H 34F2H 7031H
10.6 Reset Device After the Flash has completed programming and verified OK, the ISP Host can use "Command Write" with Reset_CPU command to wake up MTV212M64i. Reg name ISPSLV ISPEN addr 0bh (w) 0ch (w) bit7 bit6 bit5 bit4 bit3 bit2 ISP Slave address Write 93h to enable ISP Mode bit1 bit0
Test Mode Condition
In normal application, users should avoid the MTV212M64i entering its test mode or writer mode, outlined as follows, adding pull-up resistor to DA8 and DA9 pins is recommended. Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0 Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1 Writer Mode: RESET=1 & DA9=0 & DA8=1
Memory Map of XFR
Reg name IICCTR IICSTUS IICSTUS INTFLG INTFLG INTEN MBUF RCABUF TXABUF SLVAADR RCBBUF TXBBUF SLVBADR DBUF ISPSLV ISPEN ADC ADC WDT DA0 DA1 Revision 0.9 addr bit7 00h (r/w) DDC2 01h (r) WadrB 02h (r) MAckIn 03h (r) TXBI 03h (w) 04h (w) ETXBI 05h (r/w) 06h (r) 06h (w) 07h (w) ENSlvA 08h (r) 08h (w) 09h (w) ENSlvB 0Ah (w) 0bh (w) 0ch (w) 10h (w) ENADC 10h (r) 18h (w) WEN 20h (r/w) 21h (r/w) bit6 WadrA Hifreq RCBI bit5 bit4 bit3 bit2 MAckO bit1 bit0 P S SlvAlsb1 SlvAlsb0 DbufI EDbufI MbufI MbufI EMbufI
SlvRWB SAckIn SLVS Hbusy SlvBMI TXAI RCAI SlvAMI SlvBMI SlvAMI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI Master IIC receives/transmits data buffer Slave A IIC receives buffer Slave A IIC transmits buffer Slave A IIC address Slave B IIC receives buffer Slave B IIC transmits buffer Slave B IIC address DDC1 transmits data buffer ISP Slave address Write 93h to enable ISP Mode SADC3 SADC2 ADC convert result WCLR WDT2 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 - 21 -
SADC1 WDT1
SADC0 WDT0
2000/11/17
MYSON TECHNOLOGY
DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 PADMOD PADMOD PADMOD OPTION OPTION XBANK PORT4 PORT5 PADMOD PADMOD PADMOD HVSTUS HCNTH HCNTL VCNTH VCNTL HVCTR0 HVCTR2 HVCTR3 INTFLG INTEN 22h (r/w) 23h (r/w) 24h (r/w) 25h (r/w) 26h (r/w) 27h (r/w) 28h (r/w) 29h (r/w) 2Ah (r/w) 2Bh (r/w) 2Ch (r/w) 2Dh (r/w) 30h (w) DA13E 31h (w) 32h (w) HIICE 33h (w) PWMF 34h (w) 35h (r/w) 38h (w) 39h (r/w) 3Ah (w) COP17 3Bh (w) COP27 3Ch (w) 40h (r) CVpre 41h (r) Hovf 42h (r) HF7 43h (r) Vovf 44h (r) VF7 40h (w) C1 42h (w) 43h (w) 48h (r/w) HPRchg 49h (w) EHPR
MTV212M64i
(Rev 0.9)
AD1E P51E P41E MIICF1 SlvAbs1 Xbnk2 Xbnk1 P42 P41 P56 P55 P54 P53 P52 P51 COP16 COP15 COP14 COP13 COP12 COP11 COP26 COP25 COP24 COP23 COP22 COP21 COP56 COP55 COP54 Hpol Vpol Hpre Vpre Hoff HF13 HF12 HF11 HF10 HF9 HF6 HF5 HF4 HF3 HF2 HF1 VF11 VF10 VF9 VF6 VF5 VF4 VF3 VF2 VF1 C0 NoHins HBpl Selft STF1 STF0 Rt1 Rt0 CLPEG CLPPO CLPW2 CLPW1 CLPW0 VPRchg HPLchg VPLchg HFchg VFchg EVPR EHPL EVPL EHF EVF
DA12E P56E IIICE DIV253
Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC 13 DA11E DA10E AD3E AD2E P55E P54E P53E P52E HLFVE HLFHE HCLPE P42E FclkE IICpass ENSCL Msel
AD0E P50E P40E MIICF0 SlvAbs0 Xbnk0 P40 P50 COP10 COP20 COP53 Voff HF8 HF0 VF8 VF0 VBpl STE Vsync EVsync
Revision 0.9
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2000/11/17
MYSON TECHNOLOGY
ELECTRICAL PARAMETERS
1. Absolute Maximum Ratings at: Ta= 0 to 70 oC, VSS=0V Name Maximum Supply Voltage Maximum Input Voltage Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature
MTV212M64i
(Rev 0.9)
Symbol VDD Vin Vout Topg Tstg
Range -0.3 to +6.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -25 to +125
Unit V V V oC oC
2. Allowable Operating Conditions
at: Ta= 0 to 70 oC, VSS=0V Name Supply Voltage Input "H" Voltage Input "L" Voltage Operating Freq.
Symbol VDD Vih1 Vil1 Fopg
Min. 4.5 0.4 x VDD -0.3 -
Max. 5.5 VDD +0.3 0.2 x VDD 15
Unit V V V MHz
3. DC Characteristics at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V Name Symbol Output "H" Voltage, open drain pin Voh1 Output "H" Voltage, 8051 I/O port pin Voh2 Output "H" Voltage, CMOS output Voh3 Output "L" Voltage Vol Power Supply Current RST Pull-Down Resistor Pin Capacitance Idd Rrst Cio
Condition Ioh=0uA Ioh=-50uA Ioh=-4mA Iol=5mA Active Idle Power-Down VDD=5V
Min. 4 4 4
Typ.
Max.
18 1.3 50 150
0.45 24 4.0 80 250 15
Unit V V V V mA mA uA Kohm pF
4. AC Characteristics at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V Name Symbol Crystal Frequency fXtal PWM DAC Frequency fDA HS input pulse Width tHIPW VS input pulse Width tVIPW HSYNC to Hblank output jitter tHHBJ H+V to Vblank output delay tVVBD VS pulse width in H+V signal tVCPW SDA to SCL setup time tDCSU Revision 0.9
Condition fXtal=12MHz fXtal=12MHz fXtal=12MHz fXtal=12MHz FXtal=12MHz - 23 -
Min. 46.875 0.3 3
Typ. 12
Max. 94.86 8 5
8 20 200
Unit MHz KHz uS uS nS uS uS ns 2000/11/17
MYSON TECHNOLOGY
SDA to SCL hold time SCL high time SCL low time START condition setup time START condition hold time STOP condition setup time STOP condition hold time tDCH tSCLH tSCLL tSU:STA tHD:STA tSU:STO tHD:STO 100 500 500 500 500 500 500
MTV212M64i
(Rev 0.9)
ns ns ns ns ns ns ns
t
SCKH
t t t
SU:STA SCKL
HD:STO
t HD:STA
t DCSU
t DCH
2
tSU:STO
Data interface timing (I C)
Revision 0.9
- 24 -
2000/11/17
MYSON TECHNOLOGY
PACKAGE DIMENSION
1. 40-pin PDIP 600 mil
52.197mm +/-0.127
MTV212M64i
(Rev 0.9)
1.981mm +/-0.254 1.270mm +/-0.254 0.457mm +/-0.127 2.540mm 15.494mm +/-0.254 13.868mm +/-0.102 1.778mm +/-0.127 0.254mm (min.) 0.254mm +/-0.102
3.81mm +/-0.127 3.302mm +/-0.254
5o~70
6o +/-3o 16.256mm +/-0.508
2. 42 pin SDIP Unit: mm Symbol A A1 B1 D E1 F eB
Dimension in mm
Min 3.937 1.78 0.914 36.78 13.945 15.19 15.24 0
Nom 4.064 1.842 1.270 36.83 13.970 15.240 16.510 7.5
Max 4.2 1.88 1.118 36.88 13.995 15.29 17.78 15
15.494mm +/0.254 13.868mm +/0.102
0.254m m +/-0.102
5o~7
0
6o +/o 16.256mm +/- 3 0.508
Revision 0.9
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2000/11/17
MYSON TECHNOLOGY
3. 44 pin PLCC Unit:
0.045*450 PIN #1 HOLE 0.180 MAX.
MTV212M64i
(Rev 0.9)
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005 0.610 +/-0.02 0.653 +/-0.003 0.500
70TYP. 0.010 0.050 TYP. 0.026~0.032 TYP. 0.070 0.653 +/-0.003 0.690 +/-0.005 0.070
Ordering Information Standard Configurations:
Prefix MTV Part Type 212M Package Type N: PDIP S: SDIP V: PLCC ROM Size (K) 64i
Part Numbers:
Prefix MTV MTV MTV Part Type 212M 212M 212M Package Type N S V ROM Size (K) 64i 64i 64i
Revision 0.9
- 26 -
2000/11/17

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